I realise this is quite an old question, but I've had the same issues with needing to put Verilog code in a Latex document. In my case I wanted it to follow the style of Notepad++, but its easy enough to change the colouring to match your preferences.

The accepted answer doesn't work for my needs as it doesn't handle verilog constants well, nor parameter names inside square brackets.

After not finding what I needed, I was able to shamelessly adapter this answer for SuperCollider to work instead with Verilog.

I've attached an example document below with the listing style declarations, which essentially extend the existing Verilog language definition to include highlighting for constants, operators, preprocessor directives, and system commands.

The only one that's a bit iffy is the / operator, which will only highlight if it has a space on either side of it - otherwise the literate that finds it was capturing the comments as well and messing those up.

Minimal example used to produce the above output:

% Packages

documentclass{article}

% Code Handling
usepackage{listings}
usepackage{xcolor}
usepackage[lighttt]{lmodern}


begin{document}


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Verilog Code Style
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
definecolor{verilogcommentcolor}{RGB}{104,180,104}
definecolor{verilogkeywordcolor}{RGB}{49,49,255}
definecolor{verilogsystemcolor}{RGB}{128,0,255}
definecolor{verilognumbercolor}{RGB}{255,143,102}
definecolor{verilogstringcolor}{RGB}{160,160,160}
definecolor{verilogdefinecolor}{RGB}{128,64,0}
definecolor{verilogoperatorcolor}{RGB}{0,0,128}

% Verilog style
lstdefinestyle{prettyverilog}{
   language           = Verilog,
   commentstyle       = color{verilogcommentcolor},
   alsoletter         = $'0123456789`,
   literate           = *{+}{{verilogColorOperator{+}}}{1}%
                         {-}{{verilogColorOperator{-}}}{1}%
                         {@}{{verilogColorOperator{@}}}{1}%
                         {;}{{verilogColorOperator{;}}}{1}%
                         {*}{{verilogColorOperator{*}}}{1}%
                         {?}{{verilogColorOperator{?}}}{1}%
                         {:}{{verilogColorOperator{:}}}{1}%
                         {<}{{verilogColorOperator{<}}}{1}%
                         {>}{{verilogColorOperator{>}}}{1}%
                         {=}{{verilogColorOperator{=}}}{1}%
                         {!}{{verilogColorOperator{!}}}{1}%
                         {^}{{verilogColorOperator{^}}}{1}%
                         {|}{{verilogColorOperator{|}}}{1}%
                         {=}{{verilogColorOperator{=}}}{1}%
                         {[}{{verilogColorOperator{[}}}{1}%
                         {]}{{verilogColorOperator{]}}}{1}%
                         {(}{{verilogColorOperator{(}}}{1}%
                         {)}{{verilogColorOperator{)}}}{1}%
                         {,}{{verilogColorOperator{,}}}{1}%
                         {.}{{verilogColorOperator{.}}}{1}%
                         {~}{{verilogColorOperator{$sim$}}}{1}%
                         {%}{{verilogColorOperator{%}}}{1}%
                         {&}{{verilogColorOperator{&}}}{1}%
                         {#}{{verilogColorOperator{#}}}{1}%
                         { / }{{verilogColorOperator{ / }}}{3}%
                         { _}{ _}{2}%
                        ,
   morestring         = [s][color{verilogstringcolor}]{"}{"},%
   identifierstyle    = color{black},
   vlogdefinestyle    = color{verilogdefinecolor},
   vlogconstantstyle  = color{verilognumbercolor},
   vlogsystemstyle    = color{verilogsystemcolor},
   basicstyle         = scriptsizefontencoding{T1}ttfamily,
   keywordstyle       = bfseriescolor{verilogkeywordcolor},
   numbers            = left,
   numbersep          = 10pt,
   tabsize            = 4,
   escapeinside       = {/*!}{!*/},
   upquote            = true,
   sensitive          = true,
   showstringspaces   = false, %without this there will be a symbol in the places where there is a space
   frame              = single
}


% This is shamelessly stolen and modified from:
% https://github.com/jubobs/sclang-prettifier/blob/master/sclang-prettifier.dtx
makeatletter

% Language name
newcommandlanguage@verilog{Verilog}
expandafterlst@NormedDefexpandafterlanguageNormedDefd@verilog%
  expandafter{language@verilog}
  
% save definition of single quote for testing
lst@SaveOutputDef{`'}quotesngl@verilog
lst@SaveOutputDef{``}backtick@verilog
lst@SaveOutputDef{`$}dollar@verilog

% Extract first character token in sequence and store in macro 
% firstchar@verilog, per http://tex.stackexchange.com/a/159267/21891
newcommandgetfirstchar@verilog{}
newcommandgetfirstchar@@verilog{}
newcommandfirstchar@verilog{}
defgetfirstchar@verilog#1{getfirstchar@@verilog#1relax}
defgetfirstchar@@verilog#1#2relax{deffirstchar@verilog{#1}}

% Initially empty hook for lst
newcommandaddedToOutput@verilog{}
lst@AddToHook{Output}{addedToOutput@verilog}

% The style used for constants as set in lstdefinestyle
newcommandconstantstyle@verilog{}
lst@Key{vlogconstantstyle}relax%
   {defconstantstyle@verilog{#1}}

% The style used for defines as set in lstdefinestyle
newcommanddefinestyle@verilog{}
lst@Key{vlogdefinestyle}relax%
   {defdefinestyle@verilog{#1}}

% The style used for defines as set in lstdefinestyle
newcommandsystemstyle@verilog{}
lst@Key{vlogsystemstyle}relax%
   {defsystemstyle@verilog{#1}}

% Counter used to check current character is a digit
newcountcurrentchar@verilog
  
% Processing macro
newcommand@ddedToOutput@verilog
{%
   % If we're in lstpkg{}' processing mode...
   ifnumlst@mode=lst@Pmode%
      % Save the first token in the current identifier to @getfirstchar
      expandaftergetfirstchar@verilogexpandafter{thelst@token}%
      % Check if the token is a backtick
      expandafterifxfirstchar@verilogbacktick@verilog
         % If so, then this starts a define
         letlst@thestyledefinestyle@verilog%
      else
         % Check if the token is a dollar
         expandafterifxfirstchar@verilogdollar@verilog
            % If so, then this starts a system command
            letlst@thestylesystemstyle@verilog%
         else
            % Check if the token starts with a single quote
            expandafterifxfirstchar@verilogquotesngl@verilog
               % If so, then this starts a constant without length
               letlst@thestyleconstantstyle@verilog%
            else
               currentchar@verilog=48
               loop
                  expandafterifnum%
                  expandafter`firstchar@verilog=currentchar@verilog%
                     letlst@thestyleconstantstyle@verilog%
                     letiteraterelax%
                  fi
                  advancecurrentchar@verilog by @ne%
                  unlessifnumcurrentchar@verilog>57%
               repeat%
            fi
         fi
      fi
      % ...but override by keyword style if a keyword is detected!
      %lsthk@DetectKeywords% 
   fi
}

% Add processing macro only if verilog
lst@AddToHook{PreInit}{%
  ifxlst@languagelanguageNormedDefd@verilog%
    letaddedToOutput@verilog@ddedToOutput@verilog%
  fi
}

% Colour operators in literate
newcommand{verilogColorOperator}[1]
{%
  ifnumlst@mode=lst@Pmoderelax%
   {bfseriestextcolor{verilogoperatorcolor}{#1}}%
  else
    #1%
  fi
}

makeatother
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% End Verilog Code Style
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


begin{lstlisting}[style={prettyverilog}]
/*
* A Testbench Example
*/

`timescale 1 ns/100 ps

module SynchronousTestBench_tb (
  input [4:0] notReally
);

// Parameter Declarations
localparam NUM_CYCLES = 50;       //Simulate this many clock cycles.
localparam CLOCK_FREQ = 50000000; //Clock frequency (in Hz)
localparam RST_CYCLES = 2;        //Number of cycles of reset at beginning.

// Test Bench Generated Signals
reg  clock;
reg  reset;

// Device Under Test
// A counter which starts at 8'hAF.
wire [7:0] count;
counter dut (
   .clock(clock     ),
   .reset(reset     ),
   
   .start(8'hAF     ),
   .count(count[7:0])
);

// Reset Logic
initial begin
   reset = 1'b1;                        //Start in reset.
   repeat(RST_CYCLES) @(posedge clock); //Wait for a couple of clocks
   reset = 1'b0;                        //Then clear the reset signal.
end

//Clock generator + simulation time limit.
initial begin
   clock = 1'b0; //Initialise the clock to zero.
end
//Next we convert our clock period to nanoseconds and half it
//to work out how long we must delay for each half clock cycle
//Note how we convert the integer CLOCK_FREQ parameter it a real
real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;

//Now generate the clock
integer half_cycles = 0;
always begin
   //Generate the next half cycle of clock
   #(HALF_CLOCK_PERIOD);          //Delay for half a clock period.
   clock = ~clock;                //Toggle the clock
   half_cycles = half_cycles + 1; //Increment the counter
   
   //Check if we have simulated enough half clock cycles
   if (half_cycles == (2*NUM_CYCLES)) begin 
       //Once the number of cycles has been reached
       half_cycles = 0;
       $stop;
       //Note: We can continue the simualation after this breakpoint using 
       //"run -continue" or "run ### ns" in modelsim.
   end
end
endmodule
end{lstlisting}

end{document}