Retrocomputing Asked on August 25, 2021
The question is about 6502 instructions that take an extra cycle when address calculation carries over into the high byte of the address. This affects addressing modes Absolute,X, Absolute,Y, Indirect,Y. I suppose it also affects the relative branches. I’m going to call such a cycle a penalty cycle (I have seen this term in various emulator source code, and there’s no better words I can think of).
Going from this document, Many instructions take a penalty cycle to manipulate the high byte of the effective address, denoted by a + in the last column. Initially, I thought that all opcodes that needed to do this incurred a penalty cycle. But the general pattern seems to be that if it needs to write something to memory, then it doesn’t incur a penalty cycle.
Why is this? Can the high byte of the effective address sometimes somehow be incremented for free? I don’t see how, because the 6502 uses its ALU to generate the carry, and also to add the carry into the high byte.
The CPU needs to do an addition of the 2-byte address after the opcode and the 8-bit unsigned displacement from X or Y register.
Since 6502 addresses are always stored as little-endian, the CPU gets the lower byte first. During the time it reads the following higher byte, it simultaneously performs addition of the lower byte just read and the contents of the index register.
If that addition results in no carry, the CPU instantly knows it does not need to update the high byte of the address. Therefore the read cycle at the correct address follows (no penalty).
When there is carry, the 6502 needs another cycle to increment the high byte of the address. During that process, the 6502 does a dummy read cycle at the incorrect address, followed by the correct read cycle (penalty).
It is obvious that there should be no 'dummy' write cycles at incorrect addresses. Therefore the 6502 always takes a 'penalty' read cycle with an (probably) incorrect address before performing the final write.
Interesting enough, the little-endianness of the 6502 made such a cycle-saving possible. Were there big-endianness, like in the 6805, there would always be a penalty in index addressing, as it happens in the 6805 itself.
So, unlike, for example, the 8080 and Z80, here the endianness actually did matter.
Correct answer by lvd on August 25, 2021
If you compare the timing of memory writing using Absolute,X (ASL, DEC, INC, LSR, ROL, ROR, STA) or Absolute,Y (STA) with their counterpart using Absolute (without indexing), you'll note that the additional cycle is always included. It's only 'optional' for reading instructions.
Example from the (original) table (abreviated):
AND (bitwise AND with accumulator)
MODE SYNTAX HEX LEN TIM
Zero Page AND $44 $25 2 3
Zero Page,X AND $44,X $35 2 4
Absolute AND $4400 $2D 3 4
Absolute,X AND $4400,X $3D 3 4+
Absolute,Y AND $4400,Y $39 3 4+
+ add 1 cycle if page boundary crossed
ASL (Arithmetic Shift Left)
MODE SYNTAX HEX LEN TIM
Zero Page ASL $44 $06 2 5
Zero Page,X ASL $44,X $16 2 6
Absolute ASL $4400 $0E 3 6
Absolute,X ASL $4400,X $1E 3 7
Making the page crossing cycle optional is an optimization only added to reading instructions, so they are the exception here.
Answered by Raffzahn on August 25, 2021
Get help from others!
Recent Questions
Recent Answers
© 2024 TransWikia.com. All rights reserved. Sites we Love: PCI Database, UKBizDB, Menu Kuliner, Sharing RPP