A proper ISA IDE interface is quite simple, but not as easy as it might sound. There are some strange corner cases you should consider for full AT compatibility. You can find schematics for ISA IDE interface adapters in service manuals of computers slightly newer than you MFM portable computer. For example, check volume II of the Compaq Deskpro 386 technical reference manual, as found here. It has the schematics for the multi I/O-board on pages 98 to 103. I do not reproduce the schematics here as I am unsure about copyright issues. While this board does use a highly integrated custom chip, that chip is nearly unneeded for the IDE port, and more importantly, the single function it does for IDE is quite straightforward.

First, I am going to give an overview on the contents of the 6 pages:

• Page 1: It has the ISA connector (and documentation and unused gates)
• Page 2: It has the I/O address decode logic and ISA buffers needed to implement a proper IDE interface (the fine print of proper is layed out later)
• Page 3 is irrelevant (it contains the FDD bit rate oscillator and the parallel port data output latch)
• Page 4 is mostly irrelevant (it contains the custom logic chip, the floppy controller and parts of the parallel port)
• Page 5 is irrelevant (it contains the serial port and the 24MHz reference oscillator for the FDD)
• Page 6: It has the IDE connector and IDE LED connector (it also has the FDD connector and the parallel port).

So all the interesting stuff is on page 2, which I will describe in detail in the remaining part of the answer.

The two bidirectional 8-bit data buffers U31 and U27 make the 16-bit ISA/IDE data buffer. There is a special case, though, which is handled by U22, a separate 8 bit line driver that only drives seven lines on the ISA bus, D0-D6, but not D7. This is meant for port 0x3F7, which has 7 bits from the IDE cable on the low 7 bits, but the disk change line on the top bit. This top bit is driven from the floppy controller. In case of the Compaq Multi I/O board, the driver for bit 7 of port 0x3F7 is U7. They separated Bit 7 from the other bits, because there is a provision to disable the hard drive interface part, but the floppy interface (which you can't disable) still needs to drive bit 7. This special handling of port 3F7 is what seperates a proper IDE interface card from a cheap one. I have no idea whether port 3F7 is actually needed though, or you can get away with not responding to 3F7 at all (which the cheap IDE CD-ROM interfaces most likely do). This 3F7 thing is the most complicated thing on the board. The bidirectional buffer U34 is not used for the IDE interface, as well as U19 (pins 11/12/13) and U17 (pins 11/12/13). U18 (pin 4/5/6), U18 (11/12/13) and U35 (11/12/13) are only needed to suppress driver enable signals in case the IDE port is disabled (by opening SW1, so WINEN* gets high). They can be replaced by short between U18 (pin 4->6), U18 (pin 13->11) and U34 (pin 5->6).

U26 is used to decode the 3Fx (or 37x) area, whereas U21 is used the 1Fx (or 17x) area. Both are needed for IDE. U25 decodes the serial port address range and U33 decodes the parallel port address range - they are unrelated for the IDE function of this card. U20 is a line driver for IDE control signals.

U25/U33 are used to buffer the ISA address lines, because the discrete decoding logic puts a considerable load on them. U32 (as inverting buffer) is used to provide the inverted form of some address lines for decoding 0 bits inside address ranges while decoding them, with a AND/NAND gate. U8 (8/9) and U2 (3/4) are open-collector inverters with pull-ups. I don't see any reason for that construction (compared to just using a totem-pole inverter), and I guess they used this construction, because they still had some spare open-collector inverters in their hex inverter chips.

U35 (1/2/3) is simple - it enables the high-byte driver on 16-bit-accesses (IO16CS* is asserted) to the 1Fx/17x range (CS1Fx* is asserted, too). U18 (1/2/3), U18 (8/9/10) and U2 (3/4) are used to detect the pattern: CS3Fx* asserted AND A0 low AND A1 high. This is intended to catch accesses to 3F6, but as A2 is not decoded, also catches accesses to 3F2 (which seems to do no harm). The output of said gates is merged with CS1Fx* by U17(8/9/10) to provide the enable signal for the low ISA/IDE data buffer.

U19 (8/9/10) performs a very important function one might miss on ones own ISA/IDE interface design: It masks A4 (which is set in all valid IDE addresses) using the inverted AEN signal from the ISA bus, to make sure that valid IDE ports are only recognized when AEN is high. This is needed to avoid false decodes during ISA DMA cycles. Of course, it is not significant how false decodes while AEN low are avoided, munging A4 is just an implementation detail, but it is significant that AEN low causes the I/O address decoders to not respond, no matter what the address lines are.

This closes the discussion of page 2. The gates U19 (1/2/3) and U19 (4/5/6) as well as U9 (8/9) and U9 (5/6) are used for floppy controller DMA interfacing and of no concern for the IDE implementation.

The LSI chip is needed to provide the 3x7RD* signal (active low, asserted on I/O reads in the 37x/3Fx area when all of A0,A1 and A2 are high). This is actually nothing more than a 3-input OR function over CS3Fx*, BIOR* (buffered IOR* from the ISA bus) and the result of a 3-input NAND over A0, A1 and A2. It can be substituted as such in a custom design.

Hints for reading the schematic:

The schematic uses AND and OR gates with inversion circles at the inputs and output at some places. An AND gate with inversion at the input and ouptut just is an OR gate. The symbol is meant to indicate that the signals handled by the gate are acutally active low (both the input and the output), so OR gate actually generates an "active-low and" of the two active-low inputs. It gets a moment to get used to it, but for me it starts making sense.

Furthermore it is helpful to know that the quadruple 2-input 74xx logic chips all have their four gates arranged like input 1/2 -> output 3; input 4/5 -> output 6, input 9/10 -> output 8 and input 12/13 -> output 11. While not every pin number in small print is readable, limiting the possiblities to these 4 sets always gets a unique valid interpretation.