How to calculate the clock cycle in relation to bytes per clock bus?

Question

In wikipedia there is the following

With the speed of instruction fetch reduced by 50% in the 8088 as
compared to the 8086, a sequence of fast instructions can quickly
drain the four-byte prefetch queue. When the queue is empty,
instructions take as long to complete as they take to fetch. Both the
8086 and 8088 take four clock cycles to complete a bus cycle; whereas
for the 8086 this means four clocks to transfer two bytes, on the 8088
it is four clocks per byte.

And the following example:

Therefore, for example, a two-byte shift or rotate instruction, which
takes the EU only two clock cycles to execute, actually takes eight
clock cycles to complete if it is not in the prefetch queue.

I don't understand how the example works

StainlessSteelRat · Accepted Answer

Internally, 8086 and 8088 are the same.  They have an 8 byte instruction queue.   When the queue is empty, processor stalls while instruction is fetched.
Difference is BIU Bus Interface Unit, which fetches bytes for 8088 and words (2 bytes) for 8086.  Each processor takes 4 clock cycles to access RAM.
If we have a fast word instruction, the 8088 will take 8 clock cycles to execute it.  The 8086 will take 6 clock cycles if the instruction is word addressed or 8 clock cycles if the instruction is across two bytes.  The wiki is assuming optimum storage.
4 clock cycles to fetch and 2 to execute.   For a word aligned instruction, the first byte tells processor the type of instruction,  and the second specifies the action.
The execution by the EU, knows the instruction is a register based instruction, so it hides execution time for 8088 and odd byte aligned 8086, which means 8 clock cycles.

How to calculate the clock cycle in relation to bytes per clock bus?

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