Electrical Engineering Asked by kakeh on January 4, 2021
Picture to Keep the Terminology Clear
I am in the plan of using ETH for inter processor communication
I need few ETH lanes to be shared between boards, i wish to avoid ETH PHY and magnetics as the interface is between two processors only.
I have few RGMII outputs coming from a TI-TDA2x which needs to be taken to a back-plane,from back plane i shall take it another board having TI-TDA2x
i want to know what is the maximum safe distance between MAC to PHY to be maintained ?
TI-TDA2X Datasheet
My Speed Requirement : 1 Gbps
MII and RMII have round-trip time restrictions, since the TX data path on MII is destination synchronous, and the RX data path on RMII is destination synchronous. Both RMII and MII hit a hard timing limit at a few hundred millimeters trace length.
RGMII on the other hand is fully source synchronous, which means it has no hard timing limit on the trace lengths. It simply becomes an exercise in signal integrity and length matching. With for example length and impedance matched coaxial cables and terminations you should be able to go quite far.
That said, SGMII or 1000BASE-X is better suited than RGMII for board-to-board ethernet backplane situations like this.
Answered by Timmy Brolin on January 4, 2021
Without reading the datasheet, 1Gigabit is 1 nanosecond. On FR-4, with Er of about 4, the 1_foot in air becomes about 1/2_foot in epoxy-fiberglass combined with air above. You may need to tolerate round trip reflections and/or ISI energy stored in the IC leadframe and bondwires and PCB vias and Silicon ESD non-linear capacitances. Thus round trip will be 1/4 foot per side, or 3" (7.5 cm). If the link has adaptive equalization, life should be very good.
Answered by analogsystemsrf on January 4, 2021
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