Electrical Engineering Asked by norandomtechie on November 26, 2021
Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive that I can use in my code that would prevent this?
Here’s an example:
module asic (...);
logic a; // this is fine
// logic a = 1; // but this is not fine
reg b = 1; // this is fine since it is not a flip-flop
always @(posedge clk, posedge rst)
if (rst)
a <= 0;
else if (b)
a <= ~a;
endmodule
I think a check like this would be really helpful in ensuring that all registers in the ASIC design have a reset. The tools I use are Verilator (for linting and simulation) and Yosys (for synthesis), but I haven’t been able to find a related option in their documentation.
Inline initialization is not good, even for the b
signal. A commercial tool I use for ASIC synthesis ignores those initializations and throws warnings.
If b
is a constant, the below would be better (still not ideal).
logic b;
assign b = 1;
I experienced failures in formal equivalence checking (RTL vs. synthesis netlist) as well, so I avoid inline initializations in design.
Answered by user154136 on November 26, 2021
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