Loading an FPGA pin at 20MHz in parallel

I’m designing a traction inverter controlled by the NI sbRIO-9627, which includes a Zynq-7020 FPGA. I am considering using a single FPGA pin to drive the external clocks of 14x ADuM7701 isolated ADCs in parallel at 20MHz. I am concerned about trace capacitance/inductance loading down the FPGA pin.

DC current

The NI sbRIO-9627 digital outputs are listed as capable of "driving ±3 mA DC loads," whereas the logic input current of the ADuM7701 is ±0.6uA (14 * 0.6uA = 8.4uA), so this should be fine.

Transmission line

According to the 1/10th rule, with ϵr=5 and f=20MHz, you’d need a 0.6708m trace to encounter any transmission line issues. However, maybe if there is a large mismatch between source and load impedances I could encounter problems.

Load impedance: From my understanding, the load impedance would be the parasitic pin capacitance, which is 10pF for the ADuM7701.

Source impedance: The NI sbRIO-9627 digital outputs "are routed with a 55 Ω characteristic trace impedance" which I would have to match, but I can’t find information about its parasitic capacitance.

I could do an LTspice simulation of the source, transmission line, and load impedances to see if there will be any issues, however I don’t know the characterstics of my PCB yet to estimate the transmission line.

Going forward

At 20MHz, should I be concerned about overloading the FPGA pin? Would the source/load impedances typically be small enough to ignore transmission line effects altogether?