Determining AXI4-stream Data FIFO size, understanding Packet Mode?

Question

I want to take a standard AXI4-stream Data FIFO IP core and use it for data frame encapsulation for both the Ethernet and TCP/UDP layers.
When packing a header onto the packets, I need to know the length of the packet itself. Let's say I'm getting a full message that is custom to my application, and I'm going to append a UDP header onto it. The design has an incoming axistream of the message itself, and the source and destination port vectors. A checksum calculator processes the incoming signal so there is a valid checksum by the time the entire frame is placed in the input FIFO. An FSM controls the transfer to the output FIFO which should have the input message plus the UDP header appended at the beginning. The steps for my FSM would be:

Wait for the entire message/UDP payload to arrive in the input FIFO. When it is done halt further writes to keep the checksum calculator valid
Write the source port byte and destination port byte from the other input vectors
Write the size of the message into the length field
Take the checksum calculator's output and write it into the checksum field
Fully drain the input FIFO into the output FIFO

Here I have an assumption: Instantiating the AXI4-stream Data FIFO with Packet Mode enabled means the FIFO will hold off on sending its data until it receives a TLAST indicating the entire packet/message is received. The Master tvalid signal will remain low until this happens. Is that right?
I know that I can just add a counter into my checksum calculator so that when the packet is received, it also contains the size of the message. This seems like a very common use case, so I want to know if there is something that inherently supports giving out a message size when the packet is complete. If I'm using my checksum calculator, I need to only allow one message in at a time so I'll AND the slave tready with the FSM tready out to the application's transmitting axistream to force stop another message coming in. I want to know if the FIFO can be set up inherently to refuse another packet until it is empty, or if that is also a behavior for Packet Mode, so that I would not need to AND the two tready signals.

Dave Tweed · Answer

PG085 doesn't say a whole lot about packet mode, but what it does say only applies to the master (output) port of the FIFO. There is no indication that the FIFO will only accept one packet at a time.
It seems to me that what you really want is a second FIFO (also in packet mode) to hold the information that you're calculating on the input side of the main FIFO. This FIFO can be much shallower,1 since it only needs to hold one block of header information for each packet in the main FIFO.
You have one FSM on the input side that computes the length and the checksum, and then pushes this information along with the source and destination bytes into this second FIFO.2
On the output side, you have a second FSM that waits until the second FIFO is ready, reads the packet header information out of it and serializes it, and then reads the corresponding data from the main FIFO and serializes that.
This eliminates the need to have only one packet in your module at a time, and also the need for the input and output processing to run in lockstep.

1 Unless you're expecting a lot of short data packets, in which case, the sizes will be similar.
2 The second FIFO could either be very wide and use only one word per header, or you could make it one byte wide and push the header information in one byte at a time, with TLAST asserted on the final byte.

Determining AXI4-stream Data FIFO size, understanding Packet Mode?

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